NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs
نویسندگان
چکیده
High throughput and low latency designs are required in m o d e r n high performance systems, especially f o r signal processing applications. Exis t ing logic f a m i l ies canno t provide both of t h e m simultaneously. W e propose a N o r m a l Process Complemen tary P a s s Trans is tor Logic (NPCPL) which can be used as a univeraal logic t o provide f i nes t grain pipelining without affecting overall latency o r increasing the area. It does n o t require any special process s teps and hence, can be Tealised in a n o r m a l process technology as against t he CPL proposed by Y a n o et a1 [2] which uses threshold voltage ad jus tmen t of selected devices. T h e des ign procedure i s described f o r (a)low latency, (b)high throughput and (c)low area requirements. In addit i o n t o t h e various advantages, it is envisioned that NPCPL designs can also be used t o build ultra-high speed pipelined s y s t e m without pipelining latches, viz., wave pipelined digital systems, where the throughput achievable i s beyond tha t permitted by the delay of a pipeline stage.
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